Various properties of oxides can be designed by controlling the microscopic structures.
We have proposed a promising way to enhance the dielectric properties by tuning the composition of multi-element oxides.

In SSDM 2004 (K. Kita et al.) we have demonstrated, a dramatic enhancement of dielectric constant of HfO₂ approaching ~30 by a crystal-structure modification of HfO₂ for the first time in the world. This is realized by doping of different oxides, such as Y₂O₃, into HfO₂ [1]. This concept enables us to design several types of novel higher-k ternary oxides including Si-doped HfO₂[2], LaYO_x [3], and LaTaO_x [4].

Rapid thermal annealing

We have started to investigate the structural control of High-k films without doping, but with an ultrafast thermal processes. Since HfO₂ has a tendency to start to crystallize in a higher-symmetric structure followed by a transformation to the monoclinic structure [5], the dielectric properties of HfO₂ is largely controllable by tuning the time and temperature.

Tuning the threshold voltage is one of the critical issues in high-k/metal gate (HK/MG) technologies. It is because the flatband voltage (VFB) of HK/MG stack shows a significant shift depending on the employed high-k materials. In 2006 (Y. Yamamoto et al., SSDM 2006, Yokohama), we have clarified that the one of the most important factor to determine the unexpected VFB shift is due to the dipole layer formation at high-k/SiO₂ interface [6].  

 The flatband voltage shifts can be explicable by considering the change of High-k/SiO₂ interface dipole layer direction/strength [6]. The formation of dipole layers is also indicated by the shift of binding energies of XPS [7].

In 2008 (K. Kita and A. Toriumi, IEDM 2008, San Francisco) we have also proposed a possible physical origin of the dipole formation at high-k/SiO₂ interface. The structural difference between two oxides will be the key factor to determine the direction / strength of the driving force to form a dipole [8]

Thermally unstable GeO₂ electrically degrade channel interface of Ge MOSFET with GeO desorption. At first, we focused on substrate dependence of GeO desorption. The figure shows temperature desorption spectrometer (TDS) signal of GeO[1]. Low temperature GeO desorption is caused by direct GeO₂/Ge interfacing, and it is caused by the reaction of Ge + GeO₂ -> 2GeO.

 GeO desorption is limited by diffusion process in GeO₂[2]. Now, we are focusing on the diffusing species by isotope marker. The figure is the GeO signal measured by thermal desorption spectrometer (TDS). Oxygen of desorbed GeO derives from top-side GeO₂ and that GeO itself is not diffusion species[3].

 Extinction coefficients of various GeO₂ estimated by spectroscopic ellipsometry. To obtain electrically excellent GeO₂/Ge interface, high pressure oxidation which thermodynamically and kinetically suppresses GeO desorption from GeO₂/Ge stack [4]. Additionally, high pressure oxygen annealing affects bulk GeO₂ film quality. Sub-gap absorption (<6 eV) level is expected to be formed by GeO desorption [3].

Electron inversion layer mobility of Ge (100) and (111) nMOSFET with GeO₂ gate stacks formed by high pressure oxidation [5]. Ge (111) should be better in terms of the lower effective mass in two dimensional inversion layer* and higher process stability [6] . The peak mobility on Ge (111) is about 1100cm²/Vs at 300K and it is 1.5 times improved compared to that of Si Universal curve.
*S. Takagi, 2003 Symposium on VLSI Technology Digest of Technical Papers

C-V characteristics of LaLuO(rare-earth oxide)/Ge MIS capacitor with high pressure oxidation. High-k gate dielectric is required for enhancement of Ge MOSFET performance by scaling. We reported advantage of rare-earth oxides on Ge from the viewpoint of interfacial electrical characteristics [7]. Furthermore, combining this Ge friendly rare-earth oxide with high pressure oxidation (through rare-earth oxide), almost ideal C-V characteristics are obtained [8]. Now we are focusing on a role of rare-earth atom in interfacial passivation.

 At metal/Ge contact, band alignment is hardly determined by work function of metal. Fermi level of metal is strongly pinned to the valence band edge of Ge, hence Schottky characteristics is observed on n-type Ge and ohmic ones on p-type Ge irrespective to metal [9]. The origin of this strong pinning has not been clarified.
*H. B. Michaelson, J. Appl. Phys. 48, 4729 (1977).

Complete junction characteristics conversion (Schottky-ohmic conversion) by ultra-thin insulator insertion at metal/Ge interface. We found out that the strong Fermi level pinning at metal/Ge interface can be easily modulated only by ultra-thin insulator insertion[10]. This is a key to understanding a guiding principle of band alignment formation at hetero junction. 

 Structure and I-V characteristics of metal source-drain Ge p- and n-MOSFET. Metal source-drain structure is effective to reduce parasitic resistance in MOSFET. Although, the strong Fermi level pinning to valence band edge of Ge makes it difficult to inject electron from metal to conduction band, the technique of ultra-thin insulator insertion enable us to metal source/drain n-MOSFET operation[10,11]. To our knowledge, this is the first demonstration.

Graphene-based devices are promising candidates for future high-speed filed effect transistors (FETs) since a high carrier mobility of more than 200,000 cm²/Vs is obtained by mechanical exfoliation of bulk graphite. Unlike Carbon nanotube, 2D shape of graphene is compatible with conventional CMOS process flow. We started to study this very interesting material.

 Raman Spectroscopy

How to prepare graphene by mechanical cleavage of bulk graphite. Click to start.
1. Graphene transfer to SiO₂/Si wafer by ultrasonic vibrator,
2. Find graphene by optical microscopy,
3. Confirmation of monolayer by Raman microscopy.

 Cross-sectional TEM (center) of multilayer graphene and AFM image (right) of graphene edge.

Electron beam (EB) lithography apparatus (left) to draw fine electrode pattern on graphene and optical micrograph (right) of graphene FET fabricated by EB lithography.

Whole picture from graphite to graphene should be recognized first!
Monolayer is different from multilayer graphene.

(Left) Layer number dependence of sheet resistivity. Sheet resistivity monotonically increases with a decrease in the layer number. “L” indicates the number of layer.

(Right) The continuous change of the normalized sheet resistivity from graphite to bilayer is governed by one unique property, i.e., the band overlap (dE).

K. Nagashio, T. Nishimura, K. Kita, & A. Toriumi, Jpn. J. Appl. Phys., 2010, 49, 051304

 Contact resistivity is expected to be one of main limiting factors.

(Left) Optical micrograph of the four-layer graphene device with six sets of four-probe configurations (#1~#6). The contact metal is Ni.

 (Right) Two types of contact resistivity (RCA & RCW) extracted by a four-probe measurement from the devices [left figure]. This result indicates that the current injection take place at the edge (red).

The trend of decreasing of the gate dielectric SiO₂ film thickness makes it difficult to extract the physical parameters of MOS devices. It is because the tunneling current leakage thorough SiO₂ as the insulating film becomes considerable when the film thickness is decreased to 1-2 nm. We are challenging to establish a precise characterization method to extract the device parameters of ultra-thin SiO₂ MOS, and to clarify their mutual relationship.